// uvm_object_utils macro — a small flip-flop, for the engineers
class diyar_seq_item extends uvm_sequence_item;
rand bit [31:0] payload;
`uvm_object_utils_begin(diyar_seq_item)
`uvm_field_int(payload, UVM_ALL_ON)
`uvm_object_utils_end
endclass
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;
I'm an engineer who lives in the seam between hardware and software. I currently lead block-level design verification for custom compute hardware at Marvell Technology, building UVM-based environments for next-generation SoCs and developing internal tools infrastructure that the broader verification team depends on day-to-day.
My background is dual-degree by design — a B.S. in Electrical and Computer Engineering and an M.S. in Computer Science from WPI, both completed in May 2025. That foundation lets me move between RTL, verification, embedded firmware, AI model implementation, and full-stack application development without context-switching costs. I'm most interested in problems where the boundary between the two layers is the actual hard part — hardware accelerators for ML, custom verification infrastructure, and embedded systems with real-time constraints.
// 02 — Experience
Experience
Marvell Technology
Senior Design Verification Engineer
Westborough, MA
Jun 2025 – Present
Lead verification engineer for block-level IP on custom compute hardware, owning the verification strategy from spec review through coverage closure.
Architect and maintain internal tools infrastructure used across the verification organization, improving developer velocity for the broader team.
Drive technical decisions on testbench architecture, coverage methodology, and reusability across subsystem and full-chip integration.
Marvell Technology
Design Verification Intern
Westborough, MA
May 2024 – Aug 2024
Built a UVM-based verification testbench for a configurable common IP block in a next-generation SoC processor.
Partnered with the design team to translate IP specifications and RTL architecture into a verification plan covering functional coverage, signal identification, constrained random stimulus, and targeted scenarios using Verdi and the standard Cadence/Synopsys toolchain.
Architected the IP-specific Vkit — sequencers, drivers, monitors, scoreboards, interfaces, agents, environments, and sequence items — with the passive components designed for reuse at subsystem and full-chip levels.
Wrote the testbench to instantiate the DUT with runtime-configurable parameters, enabling multiple IP instances to be initialized and exercised in a single test environment.
ABB
ECE R&D Engineer Intern
Bloomfield, CT
May 2023 – Aug 2023
Worked on an agile R&D team developing diagnostic circuit breakers across high and low amperage product lines.
Collaborated across Material, Prototype, High-Current, Manufacturing, and Electrical labs to develop and test breakers built on Renesas MCUs using the e2 studio toolchain.
Analyzed and rewrote legacy diagnostic algorithms to differentiate arcing types, classify severity levels, and enable mode switching, all while meeting UL specifications.
Released the product with a fully configured UI bridging back-end MCU output to the field engineer's front-end view.
// 03 — Projects
Projects
[ HARDWARE / ML ]
FPGA Super Resolution
Major Qualifying Project, WPI · Sep 2024 – May 2025
Hardware-accelerated real-time image upscaling on a Xilinx KV260 Kria FPGA. With a five-engineer team, I helped build, train, and harden CNN and k-NN upscaling models, then translated them into custom RTL IP cores that run in parallel on the board's programmable logic. Designed companion hardware for image dispatch, gridding, reassembly, and on-board memory management. Co-authored a paper submitted for publication.
VerilogVivadoCNNKNNKV260 KriaPythonJupyter
[ SYSTEMS / FIELD ]
Lyon Arboretum Wayfinding System
Interactive Qualifying Project, University of Hawaiʻi · Jan 2024 – Mar 2024
Led a four-engineer team designing an end-to-end wayfinding and signage system for the University of Hawaiʻi's Lyon Arboretum, helping visitors engage with one of the world's most concentrated collections of endangered plants. Iterated maps, trails, and signage over eight weeks of visitor and staff feedback, and authored SOPs and templates so arboretum staff could keep extending the system after we left.
UX ResearchSystems DesignField Work
[ FULL-STACK / TEAM ]
Brigham and Women's Hospital Navigation App
WPI Software Engineering · Mar 2023 – May 2023
Scrum master and full-stack lead for a ten-engineer team building a hospital-wide application for Brigham and Women's. Coordinated three sub-teams (back-end, front-end, algorithms) via Jira and shipped features including an interactive A*-based pathfinding map, a full building/map editor, kiosk automation, face-ID access modifier, robot navigation, broadcast messaging, and a tiered-access database UI for staff.
JavaJavaFXSQLAWSA* SearchAgile
// 04 — Skills
Skills
└ Hardware & Verification
SystemVerilog
Verilog
UVM
Verdi
Vivado
Logisim
MultiSim
TinkerCAD
RTL design
Functional coverage
Constrained random verification
FPGA prototyping
└ Software & Languages
C
C++
C#
Java
Python
JavaScript
JSON
MATLAB
Simulink
└ Tools & Platforms
Linux
Git
GitHub
VSCode
Jira
Renesas e2 studio
J-Link
AutoCAD
Agile/Scrum
// 05 — Education
Education
Worcester Polytechnic Institute
Worcester, MA · 2021 – 2025
M.S. Computer Science (May 2025) — concentration in artificial intelligence: deep learning, CNNs and RNNs, support vector machines, regression, and large language models.
B.S. Electrical and Computer Engineering (May 2025) — concentration in computer engineering, microelectronics, and embedded systems; RTL design and verification, IC design, microprocessor design.
United World College East Africa
2019 – 2021
IB Diploma. Higher Level: Literature, Mathematics: Analysis and Approaches, Biology, Economics. Extended Essay on regional oil-market dynamics.
// 06 — Awards & Recognition
Awards & Recognition
Spring 2022 – Spring 2025
Dean's List, every semester (eight consecutive).
Spring 2022
Founder, National Society of Leadership and Success (NSLS), WPI Chapter.
// 07 — Contact
Contact
I'm always open to interesting conversations — whether that's about verification methodology, FPGA acceleration for ML, or just the right way to architect a testbench. The fastest way to reach me is email.